1. Field of the Invention
The field of the present invention relates to an improved method and apparatus for interconnection of microcircuit elements on a wafer to enable high reliability wafer scale integration and a new improved memory circuit.
2. Prior Art
Present methods of semiconductor fabrication typically require that a plurality of identical semiconductor elements or circuits be fabricated on a single wafer substrate through a series of process steps. At the conclusion of the fabrication process, the elements or circuits are tested and the defective elements identified. The wafer is then scored and diced into individual parts, each containing a complete circuit. These operable parts are then packaged to provide external connections and appropriate environmental protection for the finished product.
It has long been realized that circuit costs as well as space and power requirements could be reduced if the operable parts or elements on the wafer could be interconnected on the wafer itself. This would reduce the necessity for circuit boards or interconnection wiring between elements. In addition, dicing would be eliminated and packaging would be relatively simple for the single wafer itself.
The variety of methods for interconnecting elements on a wafer which have been suggested these include a metalization step after the circuits or elements of the wafer are tested to interconnect the operable elements on the wafer. The disadvantage of this method is that a different mask is required for each individual wafer, due to the fact that not only the yield may be different for a given wafer but defects are randomly created. The production of a unique mask for each wafer not only greatly increases the cost of the finished product but is considerably time consuming thereby slowing the manufacturing process. Other wafer integration schemes such as described in U.S. Pat. No. 3,940,740, provide for spare rows and columns on the wafer matrix for appropriate sparing of defective elements. The disadvantage of this configuration is that an entire row of elements must be provided to spare a single defective matrix element. Also patents such as U.S. Pat. No. 4,092,733 provide schemes where multiple elemental structures may be interconnected. However, no particular circuitry is described to implement any particular memory structure. A preferred method would be one where spare memory elements may be inserted in the matrix on a random basis to allow all spare elements to be used, a technique which has not yet been perfected in the prior art.